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www.siliconstandard.com 1 of 11 SS4035G 1/09/2006 rev.3.01 two-cell li-ion and li-polymer charge management ic charge management for two-cell li-ion or li-polymer battery packs individual cell monitoring - avoids over-charging pin-selectable charging current product summary features cell-balancing control circuit - maximizes pack useful life optional external thermistor monitors the pack temperature conditioning charging for reviving deeply discharged cells timer function available to limit the charging time pb-free, rohs compliant so-20 package the SS4035G is a charging control ic designed for battery packs with two cells in series. when multiple cells in a battery pack are connected in series, the weakest cell determines the overall pack capacity. the SS4035G has a cell-balance control circuit to solve this problem, and monitors the voltage of each cell to ensure that no cell is over-charged. the pulse width modulation (pwm) output can be used as either a linear or switching charge-control circuit. three digital input pins determine the charge current. all these features make the charging circuit design easy and flexible. the SS4035G continuously monitors each cell voltage, cell current and the battery temperature. any unspecified condition will stop the charging to protect the battery cells. an external negative- temperature-coefficient thermistor is used as a sensor to monitor the battery pack temperature. to be safe, charging is suspended if the voltage of the temperature sense input pin is higher than min temp threshold (vtmin) or lower than max temp threshold (vtmax). when the battery temperature is within the safe zone, the SS4035G charges the battery in three phases: pre-charging, constant-current, or constant-voltage. if the voltage of the temperature sense input pin is higher than low temp threshold (vtlow), or the battery voltage is less than 3.1v, the SS4035G pre-charges the battery with a low current. after the precharging, the SS4035G applies a constant current to the battery. the value of this constant current is determined by the levels of pins s1, s2 and s3 during power up. when the battery voltage is above the threshold, the SS4035G begins constant-voltage charging until the battery is fully charged. the battery is fully charged when the current drops down to the termination threshold. when the cell voltage is higher than the balancing threshold (vbal), the cell balancing circuit is triggered if one cell voltage is higher than the other by more than 0.02v. description
www.siliconstandard.com 2 of 11 ss 40 35g 1/09/2006 rev.3.01 pin description pin name pin no i/o description cled 1 o charge control led cfled 2 o charge full control led testin 3 i te st input testout 4 o test output cctl 5 o charging control, pwm output n/c 6 o not connected res 7 i reset gn d 8 g ground t 9 a temperature-sense voltage input i 10 a current-sense voltage input v1 11 a cell 1 v oltage (low side) v2 12 a cell 2 v oltage (high sid e) v dd 13 p oper ating voltag e input rosc 14 i frequency control resistor s3 15 i sele ction no.3 avdd 16 p operating voltage for analog circuit ba1 17 o balan cing control for ce ll 1 ba2 18 o balan cing control for ce ll 2 s1 19 i sele ction no.1 s2 20 i sele ction no.2 cled 1 20 s2 cfled 2 19 s1 testin 3 18 ba2 testout 4 17 ba1 cctl 5 16 avdd n/c 6 15 s3 res 7 14 rosc gnd 8 13 vdd t 9 12 v2 i 10 11 v1 pin configuration
www.siliconstandard.com 3 of 11 ss 40 35g 1/09/2006 rev.3.01 absolute maximum ratings dc voltage ???? - 0.3v to +7.0v storage temper ature??? ?... -55c to +125c i /o voltage?... (gnd-0.3v ) to (v dd +0.3v) operating temperature???... -40c to +85c * stresses beyond those listed as ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. exposure to the absolute maximum rating condition for an extended period may affect device reliability. electrical characteristics v dd = 4.5v ? 5.5v, gnd = 0v, t a = 25c,, f osc = 8mhz, unless otherwise specified. parameter symbol min. typ. max unit condition operating v oltage v dd 4.5 5.0 5.5 v operating current i op - 1.5 2 ma no load, no adc standby current i sb - - 1 ua no load, no adc, no wdt, no lvr input low voltage v il1 gnd - 0.2* v dd v all i/o, except res input low voltage v il2 gnd - 0.15* v dd v res input high voltage v ih1 0.8*v dd - v dd v all i/o, except res input high voltage v ih2 0.85*v dd - v dd v res input leakage current i il -1 - 1 ua input pins, vin=v dd or gnd output high voltage v oh v dd -0.7 - - v all i/o, i oh =-10ma output low voltage v ol - - gnd +0.6 v all i/o, i ol =20ma analog input ain gnd v dd v t, i, v1, v2
www.siliconstandard.com 4 of 11 ss 40 35g 1/09/2006 rev.3.01 electrical characteristics (continued) v dd = 5v, gnd = 0v, t a = 25c, f osc = 8mhz, r sens =100mw, unless otherwise specified. parameter symbol min. typ. max unit description voltage control pre-ch arge threshold v low - 3.10 - v cc/cv threshold v cv - 4.135 - v switch to cv mode above this value maximum cell voltage v max - 4.235 - v balancing threshold v bal - 4.135 - v bad b attery threshold v bad - 0.5 - v difference between cell1 and cell 2 voltage temperature sensing min temp t hres hold v tun - 4.31 - v suspend charging if greater than this value low temp t hreshold vt low - 3.82 - v precharge if greater th a n this value high temp threshold vt high - 1.90 - v decrease current if less than this value max temp t hreshold vt over - 1.54 - v suspend charging if less than this value resume temp thresh old vt rsm - 2.10 - v after maximum temperature is reached, resume charging if greater than this value. current control precharge current i pre - 300 - ma taper current i taper - 250 - ma fully charged if the taper current is below t his v alue. time control maximum charge time t chg 340 min
www.siliconstandard.com 5 of 11 ss 40 35g 1/09/2006 rev.3.01 functional description pbv ppv pmv i tc pev plv pcv i cv i cc trickle charge cc charge cv charge finished capacity figure 1. typical charge profile a well-known li-ion charge algorithm is used by the the ss4035 g to control the charging. figure 1 shows shows the typical charge profile. figure 2 is the control flow chart. during the process of charging, the ss4035 g continuously monitors each cell voltage, current and the battery temperature. any unqualified condition will stop the charging to protect the battery cells.
www.siliconstandard.com 6 of 11 ss 40 35g 1/09/2006 rev.3.01 figure 2. control flow chart yes yes power on reset start timer measure v1, v2, i, t temperature ok? vcell, vpack ok? no time out? vpack > vlow ? cells unbalance ? vpack > vcv? i < itaper ? i regulate pre-charge i regulate constant current v regulate constant voltage set charge-full end of charge turn on balancing yes no yes yes no no no no
www.siliconstandard.com 7 of 11 ss 40 35g 1/09/2006 rev.3.01 current and temperature sensing 6.8k w avdd 16 cctl 5 vdd 13 testin 3 cled 1 testout 4 cfled 2 v2 12 s3 15 ba2 18 s2 20 v1 11 s1 19 ba1 17 res 7 fc 6 rosc 14 t 9 gnd 8 i 10 SS4035G 50m w vdd vdd 10k w figure 3 shows the current sense and temperature sensor. when a 103at thermistor and a 6.8k resistor detect circuit. the SS4035G monitors the charging are used as recommended, the maximumum current by sensing at pin i (10) the voltage drop temperature, high temperature, resume temperature, across a small resistor, connected between vss low temperature and minimum temperature are (battery negative) and gnd (charger ground). the 60c, 50c, 45c, 5c and 10c respectively. the value of this resistor should be between 50m w value of the resistor must be changed if a different and 150m w . to detect the temperature, a negative thermistor is used. to disable temperature sensing, temperature coefficient thermistor is used as a . pin t (9) must be connected to v dd . c ell voltage detection and balancing control 10k w 10kw p-channel mosfet npn npn avdd 16 cctl 5 vdd 13 testin 3 cled 1 testout 4 cfled 2 v2 12 s3 15 ba2 18 s2 20 v1 11 s1 19 ba1 17 res 7 fc 6 rosc 14 t 9 gnd 8 i 10 SS4035G r b r b 470k w r13 51k w 51k w r14 51k w vdd figure 4 shows the cell voltage detection and cell guarantees that the input voltage on pin v2 (12) will balancing circuit. the pack voltage is divided by two not exceed vdd. when the cell voltage is above the (by using equal value resistors, r13 and r14). this ?balancing threshold?, balance control is activated. figure 4. voltage sense and balancing control figure 3. current sense and temperature sensor 103at p-channel mosfet 470k w
www.siliconstandard.com 8 of 11 ss 40 35g 1/09/2006 rev.3.01 if any cell voltage is greater than the other by 0.02v transistor and sends a small current through resistor or more, the corresponding balance control output rb. this slows down charging of the corresponding cell. goes high. it then turns on the corresponding by-pass the balance circuit turns off when the cells are balanced. charging control avdd 16 cctl 5 vdd 13 testin 3 cled 1 testout 4 cfled 2 v2 12 s3 15 ba2 18 s2 20 v1 11 s1 19 ba1 17 res 7 fc 6 rosc 14 t 9 gnd 8 i 10 u? SS4035G 1k w 3.3k w 10k w npn cap v+ vb+ vdd figure 5 shows the linear charger mode for the mosfet which is operating in the active region. SS4035G. the output of pin cctl (5) is a pulse- this p-channel mosfet must be chosen carefully width modulated (pwm) signal. this signal is to handle the required power dissipation. translated to a dc voltage to control the p-channel digital controls avdd 16 cctl vdd 13 testin cled 1 testout cfled 2 v2 s3 15 ba2 s2 20 v1 s1 19 ba1 res 7 fc rosc 14 t gnd 8 i SS4035G 3k 3k 47k 8.6k led led 1nf vdd figure 6 shows the connections for the digital pins have internal pull-ups. table 1 shows the options for the SS4035G. selection pins s1, s2 and s3 for selecting the required voltage for isense. figure 5. charging control figure 6. current selection and logic control p-channel mosfet
www.siliconstandard.com 9 of 11 ss 40 35g 1/09/2006 rev.3.01 s3 s2 s1 i sense voltage l l l 240 mv l l h 200 mv l h l 160 mv l h h 120 mv h l l 40 mv h l h 60 mv h h l 80 mv h h h 100 mv res (7) is the reset control. a low voltage on this pin will reset the device. connect to v dd if not used. rosc (14) is the frequency control input. for the ss4053g to work at 8mhz, this pin must be connected to v dd through an 8.6kw resistor. cled (1) is the "charging" indication output. this pin goes low when the SS4035G is operating. cfled (2) is the "fully charged" indication output. this pin goes low when the battery is fully charged. table 1. current selection table
www.siliconstandard.com 10 of 11 ss 40 35g 1/09/2006 rev.3.01 physical dimensions (units: inches) 0.10mm c seating plane so -20 h g q b a c 1 c e f d min. nom. max. a 0.394 - 0.419 b 0.290 - 0.300 c 0.014 - 0.020 c1 0.480 - 0.520 d 0.092 - 0.104 e - 0.050 - f 0.004 - - g 0.032 - 0.038 h 0.004 - 0.012 q 0 o - 10 o dimensions in inches symbol
information furnished by silicon standard corporation is believed to be accurate and reliable. however, silicon standard corporation makes no guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. silicon standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. no license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of silicon standard corporation or any third parties. www.siliconstandard.com 11 of 11 ss 40 35g 1/09/2006 rev.3.01

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